NSF award 2604733 · University of California-San Diego

SaTC: TTP: Medium: Hardware Intellectual Property Protection through Hybrid ASIC/TRAP Integrated Circuit Design

Final report due

29 March 2028

in 528 days · The award ends on 30 November 2027.

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Decide about an extension2 Aug 2027in 288 days
award ending 2027-11-30 · Research.gov
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Extension request16 Oct 2027in 363 days
award ending 2027-11-30 · Research.gov
PAPPG 24-1: “at least 45 days prior to the end date”
No-cost extension notice20 Nov 2027in 398 days
award ending 2027-11-30 · Research.gov
PAPPG 24-1: “at least ten calendar days prior to the end date”
Final report due29 Mar 2028in 528 days
award ending 2027-11-30 · Research.gov
PAPPG 24-1: “no later than 120-days following the end date of the award”
Project outcomes report due29 Mar 2028in 528 days
award ending 2027-11-30 · Research.gov
PAPPG 24-1: “no later than 120 days following the end date”
Award is closed out29 Mar 2028in 528 days
award ending 2027-11-30 · Research.gov
PAPPG 24-1: “financially closed out 120 days after their expiration date”

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NSF lists this award's end date as 30 November 2027.
NSF rules say the final report is due no later than 120 days after that.
So the final report is due by 29 March 2028.

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Award card

Award number: 2604733
Period of support: 15 Dec 2025 – 30 Nov 2027
Amount: $900,000
Awardee: University of California-San Diego, LA Jolla, CA
Program: Secure &Trustworthy Cyberspace
Directorate: CSE

Abstract

As the semiconductor industry transitioned from an in-house fabrication model to a third-party foundry model, it provided widespread access to cutting edge technology at affordable cost and accelerated development of advanced electronic circuits. At the same time, it introduced new concerns regarding protection of the intellectual property of these electronic circuits, whose blueprints must now be shared with…

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