NSF award 2504228 · Virginia Commonwealth University

Collaborative Research: FET: MEDIUM: PRocessor In Memory Architecture based on Topological Electronics (PRIMATE)

Final report due

29 December 2029

in 1,168 days · The award ends on 31 August 2029.

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award ending 2029-08-31 · Research.gov
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Extension request17 Jul 2029in 1003 days
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PAPPG 24-1: “at least 45 days prior to the end date”
No-cost extension notice21 Aug 2029in 1038 days
award ending 2029-08-31 · Research.gov
PAPPG 24-1: “at least ten calendar days prior to the end date”
Final report due29 Dec 2029in 1168 days
award ending 2029-08-31 · Research.gov
PAPPG 24-1: “no later than 120-days following the end date of the award”
Project outcomes report due29 Dec 2029in 1168 days
award ending 2029-08-31 · Research.gov
PAPPG 24-1: “no later than 120 days following the end date”
Award is closed out29 Dec 2029in 1168 days
award ending 2029-08-31 · Research.gov
PAPPG 24-1: “financially closed out 120 days after their expiration date”

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NSF lists this award's end date as 31 August 2029.
NSF rules say the final report is due no later than 120 days after that.
So the final report is due by 29 December 2029.

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Award card

Award number: 2504228
Period of support: 1 Sep 2025 – 31 Aug 2029
Amount: $307,000
Awardee: Virginia Commonwealth University, Richmond, VA
Program: FET-Fndtns of Emerging Tech
Directorate: CSE

Abstract

In the “Beyond Moore’s Law” era with increasing edge intelligence, domain-specific computers in heterogeneous fabrics will rule the roost. Algorithms accelerating NP-hard (i.e., provably complex) applications or pre-compute processes that do not demand exact precision will run on tailored hardware. The hardware performance, rather than the algorithmic or software efficiency, may dictate solution speed, energy cost,…

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